To make a high current, high voltage, low on-resistance, vertical SiC power MOSFET has, so far, been impractical, at least in part, due to the poor surface mobility of electrons in the inversion layer. Recently, some processing techniques have been developed on a lateral MOSFET structure, which result in an improved surface electron mobility. However, a power MOSFET structure may involve additional processing including, for example, anneals at temperatures of greater than 1500° C. for the activation of p-type dopants, for example, p-well/p+ contact/p-Junction Termination Extension (JTE) implants. Such anneals may have detrimental impact on the performance of power MOSFETs fabricated using such techniques.
A number of silicon carbide power MOSFET structures have been described in the literature. See e.g. U.S. Pat. No. 5,506,421; A. K. Agarwal, J. B. Casady, L. B. Rowland, W. F. Valek, M. H. White, and C. D. Brandt, “1.1 kV 4H—SiC Power UMOSFET's,” IEEE Electron Device Letters, Vol. 18, No. 12, pp. 586-588, December 1997; A. K. Agarwal, J. B. Casady, L. B. Rowland, W. F. Valek and C. D. Brandt, “1400 V 4H—SiC Power MOSFETs,” Materials Science Forum Vols. 264-268, pp. 989-992, 1998; J. Tan, J. A. Cooper, Jr., and M. R. Melloch, “High-Voltage Accumulation-Layer UMOSFETs in 4H—SiC,” IEEE Electron Device Letters, Vol. 19, No. 12, pp. 487-489, December 1998; J. N. Shenoy, J. A. Cooper and M. R. Melloch, “High-Voltage Double-Implanted Power MOSFET's in 6H—SiC,” IEEE Electron Device Letters, Vol. 18, No. 3, pp. 93-95, March 1997; J. B. Casady, A. K. Agarwal, L. B. Rowland, W. F. Valek, and C. D. Brandt, “900 V DMOS and 1100 V UMOS 4H—SiC Power FETs,” IEEE Device Research Conference, Ft. Collins, Colo., June 23-25, 1997; R. Schörner, P Friedrichs, D. Peters, H. Mitlehner, B. Weis and D. Stephani, “Rugged Power MOSFETs in 6H—SiC with Blocking Capability up to 1800 V,” Materials Science Forum Vols. 338-342, pp. 1295-1298, 2000; V. R. Vathulya and M. H. White, “Characterization of Channel Mobility on Implanted SiC to determine Polytype suitability for the Power DIMOS structure,” Electronic Materials Conference, Santa Barbara, Calif., Jun. 30-Jul. 2, 1999; A. V. Suvorov, L. A. Lipkin, G. M. Johnson, R. Singh and J. W. Palmour, “4H—SiC Self-Aligned Inplant-Diffused Structure for Power DMOSFETs,” Materials Science Forum Vols. 338-342, pp. 1275-1278, 2000; P. M. Shenoy and B. J. Baliga, “The Planar 6H—SiC ACCUFET: A New High-Voltage Power MOSFET Structure,” IEEE Electron Device Letters, Vol. 18, No. 12, pp. 589-591, December 1997; Ranbir Singh, Sei-Hyung Ryu and John W. Palmour, “High Temperature, High Current, 4H—SiC Accu-DMOSFET,” Materials Science Forum Vols. 338-342, pp. 1271-1274, 2000; Y. Wang, C. Weitzel and M. Bhatnagar, “Accumulation-Mode SiC Power MOSFET Design Issues,” Materials Science Forum Vols. 338-342, pp. 1287-1290, 2000; and A. K. Agarwal, N. S. Saks, S. S. Mani, V. S. Hegde and P. A. Sanger, “Investigation of Lateral RESURF, 6H—SiC MOSFETs,” Materials Science Forum Vols. 338-342, pp. 1307-1310, 2000.
The existing SiC structures can be divided into three categories: (1) Trench or UMOSFET, (2) Vertical Doubly Implanted MOSFET (DIMOSFET), and (3) Lateral Diffused MOSFET (LDMOSFET). These structures are shown in FIGS. 1A, 1B, 1C and 1D. With the Trench MOSFET illustrated in FIG. 1A, however, it may be difficult to achieve a high breakdown voltage and a reproducible high inversion layer mobility along the sidewalls of the trench. Consequently, the on-resistance may become very high, which may render the structure impractical. The lateral DMOSFET, illustrated in FIGS. 1C and 1D, may suffer from high electric field in the gate oxide and higher on-resistance as compared to the vertical DIMOSFET for a given breakdown voltage.
The vertical DIMOSFET structure, illustrated in FIG. 1B, is a variation of the Diffused (DMOSFET) structure employed in silicon technology. Typically, the p-wells are implanted with Al or Boron, the source regions (n+) are implanted with nitrogen or phosphorus, and the p+ regions are usually implanted with Al. The implants are activated at temperatures between 1400° C.-1700° C. The contacts to n+ layers are made with nickel (Ni) and annealed and the contacts to p+ are made by Ni, Ti or Ti/Al. Both contacts are annealed at high temperatures. The gate dielectric is, typically, either thermally grown (Thermal SiO2) or deposited using Low Pressure Chemical Vapor Deposition (LPCVD) technique and subsequently annealed in various ambients. The deposited dielectric may be SiO2 or an Oxide/Nitride/Oxide (ONO) stack. One difficulty with the DIMOSFET structure may be the poor mobility of inversion layer electrons, which can result in a very high on-resistance. The cause of such a problem has been attributed to a high density of interface states near the conduction band edge as shown in FIG. 2. See R. Schorner, P. Friedrichs, D. Peters, and D. Stephani, “Significantly Improved Performance of MOSFETs on Silicon Carbide using the 15R—SiC Polytype,” IEEE Electron Device Letters, Vol. 20, No. 5, pp. 241-244, May 1999.
The interface states near the conduction band edge tend to trap the otherwise free electrons from the inversion layer leaving a relatively small number of free electrons in the inversion layer. Also the trapped electrons may create negatively charged states at the interface which coulomb scatter the free electrons. The reduced number of free electrons and the increased scattering may reduce the conduction of current from source to drain, which may result in low effective mobility of electrons and a high on-resistance. Several factors have been attributed to the high density of states near the conduction band edge: (1) carbon or silicon dangling bonds, (2) carbon clusters, and (3) Si—Si bonds creating a thin amorphous silicon layer at the interface. See S. T. Pantelides, “Atomic Scale Engineering of SiC Dielectric Interfaces,” DARPA/MTO High Power and ONR Power Switching MURI Reviews, Rosslyn, Va., Aug. 10-12, 1999 and V. V. Afanas'ev, M. Bassler, G. Pensl, and M. Schulz, “Intrinsic SiC/SiO2 Interface States,” Phys. Stat. Sol. (a), Vol. 162, pp. 321-337, 1997.
In addition to the high density of interface states, several other mechanisms have also been attributed to the poor mobility of inversion layer electrons: (1) Al segregating out of the Al-doped, p-type SiC, and (2) Surface roughness created by the high temperature activation of implanted impurities. See S. Sridevan, P. K. McLarty, and B. J. Baliga, “On the Presence of Aluminum in Thermally Grown Oxides on 6H-Silicon Carbide,” IEEE Electron Device Letters, Vol. 17, No. 3, pp. 136-138, March 1996 and M. A. Capano, S. Ryu, J. A. Cooper, Jr., M. R. Melloch, K. Rottner, S. Karlsson, N. Nordell, A. Powell, and D. E. Walker, Jr., “Surface Roughening in Ion Implanted 4H-Silicon Carbide,” Journal of Electronic Materials, Vol. 28, No. 3, pp. 214-218, March, 1999. Researchers from Purdue University have concluded that a direct correlation exists between the inversion layer electron mobility and the implant activation temperature. Such research has concluded that lower implant activation temperature (1200° C.) leads to higher electron mobility and higher activation temperature (1400° C.) results in poor electron mobility. See M. K. Das, J. A. Cooper, Jr., M. R. Melloch, and M. A. Capano, “Inversion Channel Mobility in 4H— and 6H—SiC MOSFETs,” IEEE Semiconductor Interface Specialists Conference, San Diego, Calif., Dec. 3-5, 1998. These results have been obtained on planar MOSFETs (FIG. 3), which do not utilize an implantation of the p-well. The p-well implanted impurity (Al or Boron) typically requires at least a 1500° C. activation temperature.
The so-called “ACCUFET” structure is shown in FIG. 4. It results in high electron mobility due to conduction across an accumulation layer instead of an inversion layer. In this structure, the p-well is implanted using Al in such a manner so as to leave a thin unimplanted n-type surface layer. This n-type layer is fully depleted due to the built-in voltage of the pn junction. However, the implant activation temperature is typically limited to 1400° C. to avoid surface roughness as indicated before. The doping of the remaining n-layer is the same as the doping of the grown n-type layer. This structure has shown high electron mobility in 6H—SiC but very poor electron mobility in 4H—SiC.
Sridevan and Alok have reported high electron mobility in 4H—SiC in a planar MOSFET on a p-type epitaxial layer (p-epi). S. Sridevan and B. Jayant Baliga, “Lateral N-Channel Inversion Mode 4H—SiC MOSFET's,” IEEE Electron Device Letters, Vol. 19, No. 7, pp. 228-230, July 1998; D. Alok, E. Arnold, and R. Egloff, “Process Dependence of Inversion Layer Mobility in 4H—SiC Devices,” Materials Science Forum Vols. 338-342, pp. 1077-1080, 2000. However, this is not a high voltage power MOSFET structure. By using p-epi, the problems associated with p-well activation and resulting surface roughness may potentially be avoided. A deposited oxide was used and the activation temperature of nitrogen implants for the source and drain regions kept to a minimum (1250° C.) to avoid surface roughness. The contacts to the source and drain regions were not annealed in order to protect the gate oxide/SiC interface. The high electron mobility has been attributed to the special wet anneal of the deposited SiO2 layer. This anneal was done at 1100° C. in N2 bubbled through de-ionized (DI) water at 98° C. for 400 min, followed by an in situ Ar anneal at 1100° C. for 60 min, followed by a 950° C. wet N2 anneal for 60 min. The anneal was performed to densify the deposited oxide and reduce the interface state density. Unfortunately, this approach suffers from reproducibility. Several groups, including researches at Rensealar Polytechnic Institute (RPI), Purdue University, and Cree, Inc. have been unsuccessful in their attempts to duplicate this result.
Another method that has been reported as showing promise is the counter-doping method. K. Ueno and Tadaaki Oikawa, “Counter-Doped MOSFET's of 4H—SiC,” IEEE Electron Device Letters, Vol. 20, No. 12, pp. 624-626, December 1999. Again, this technique has been implemented on planar MOSFETs without the p-well implant. This is not a high voltage power MOSFET structure. By using p-epi, the problems associated with p-well activation and resulting surface roughness may be avoided. In the counter-doping method, a thin layer of n-type impurity such as Nitrogen is implanted between the source and drain. The implant is activated at a low temperature (1300° C.) to avoid surface roughness. The doping density of the n-type region can be controlled by controlling the dose and energy of the n-type implant. By relaxing the surface field with this implant, higher channel mobilities have been reported.
Recently, annealing of a thermal oxide in a nitric oxide (NO) ambient has shown promise in a planar 4H—SiC MOSFET structure not requiring a p-well implant. See M. K. Das, L. A. Lipkin, J. W. Palmour, G. Y. Chung, J. R. Williams, K. McDonald, and L. C. Feldman, “High Mobility 4H—SiC Inversion Mode MOSFETs Using Thermally Grown, NO Annealed SiO2,” IEEE Device Research Conference, Denver, Colo., Jun. 19-21, 2000 and G. Y. Chung, C. C. Tin, J. R. Williams, K. McDonald, R. A. Weller, S. T. Pantelides, L. C. Feldman, M. K. Das, and J. W. Palmour, “Improved Inversion Channel Mobility for 4H—SiC MOSFETs Following High Temperature Anneals in Nitric Oxide,” IEEE Electron Device Letters accepted for publication, the disclosures of which are incorporated by reference as if set forth fully herein. This anneal is shown to significantly reduce the interface state density near the conduction band edge. G. Y. Chung, C. C. Tin, J. R. Williams, K. McDonald, M. Di Ventra, S. T. Pantelides, L. C. Feldman, and R. A. Weller, “Effect of nitric oxide annealing on the interface trap densities near the band edges in the 4H polytype of silicon carbide,” Applied Physics Letters, Vol. 76, No. 13, pp. 1713-1715, March 2000, the disclosure of which is incorporated herein as if set forth fully. High electron mobility (35-95 cm2/Vs) is obtained in the surface inversion layer due to the improved MOS interface.
Unfortunately, NO is a health hazard having a National Fire Protection Association (NFPA) health danger rating of 3, and the equipment in which post-oxidation anneals are typically performed is open to the atmosphere of the cleanroom. They are often exhausted, but the danger of exceeding a safe level of NO contamination in the room is not negligible.
Growing the oxide in N2O is possible. J. P. Xu, P. T. Lai, C. L. Chan, B. Li, and Y. C. Cheng, “Improved Performance and Reliability of N2O-Grown Oxynitride on 6H—SiC,” IEEE Electron Device Letters, Vol. 21, No. 6, pp. 298-300, June 2000, the disclosure of which is incorporated by reference as if set forth fully herein. Post-growth nitridation of the oxide on 6H—SiC in N2O at a temperature of 1100° C. has also been investigated by Lai et al. P. T. Lai, Supratic Chakraborty, C. L. Chan, and Y. C. Cheng, “Effects of nitridation and annealing on interface properties of thermally oxidized SiO2/SiC metal-oxide-semiconductor system,” Applied Physics Letters, Vol. 76, No. 25, pp. 3744-3746, June 2000, the disclosure of which is incorporated by reference as if set forth fully herein. However, Lai et al. concluded that such treatment deteriorates the interface quality which may be improved with a subsequent wet or dry anneal in O2 which may repair the damage induced by nitridation in N2O. Moreover, even with a subsequent O2 anneal, Lai et al. did not see any significant reduction in interface state density as compared to the case without nitridation in N2O. However, this work utilized 6H—SiC and it is not clear whether it would work on 4H—SiC, since many improvements to 6H—SiC MOSFETs have not previously resulted in any significant improvement in 4H—SiC MOSFETs.